Semiconductors today have millions of logic gates on the device. As transistor and semiconductor technology is evolves, the number of logic gates on the device will increase. It is important to test all of the logic gates on a device in a reasonable period of time, and this will become more challenging for newer generation semiconductor devices.
In semiconductor test methodologies, Automatic Test Pattern Generation (ATPG) and scan test are the two most commonly used techniques for testing logic gates on a semiconductor device. The scan test volume (the amount of data required to program the scan test) is increasing as technology scaling increases the number of gates on the device. More test patterns (data) are also required to detect more subtle defects which also result from technology scaling. These factors require significantly more test patterns to detect small delay defects, N-detects and bridging faults simply to achieve the quality target. Additionally, ATPG is becoming more constrained by power requirements during shift and capture cycles, which also results in more test patterns. When the compression ratio stays flat, ATPG testing does not scale.
Scan testing is facing its own challenges. The number of scan channels available on a given semiconductor device is fewer on newer devices, but the test data volume is increasing with the number of logic gates to be tested. Most of the pins on a semiconductor device are serial input or output pins. At high speed and/or for high performance semiconductor devices, the serial input and output pins are connected to Serializer-Deserializer (SerDes) interfaces. The available pins for scan testing are limited to the lower speed “digital pins”. SerDes pins cannot be used for scan testing because even a single fan-out from the high speed signals for scan channels would affect system integrity and cause performance degradation. Using a conservative approach, the design engineers would not allow test engineers to add circuitry for scan connections.
Scan test time is an important factor in component cost and the ability to deliver large numbers of components in a timely manner. Scan data compression techniques known in the industry have been successful in reducing the scan test time but do not help when the compression ratio stays flat around 50× and do not scale when the number of scan channels available are reduced. In the case described above, fewer test channels mean longer test times, higher costs and reduced ability to deliver parts on time.